1. Field of the Invention
The present invention relates to a semiconductor LSI circuit design for testing a circuit. In particular, the invention relates to a semiconductor LSI circuit including scan circuits, a scan circuit system, and a scanning test system, which are applied to circuit design for a scan circuit shifting test.
2. Description of the Related Art
Generation of test patterns for testing complex semiconductor LSI circuits requires a significant part of the time needed for designing an LSI. A combination of test patterns generated for a designed function test that allows a high fault detection rate may be selected and used for a fabrication test. However, there is a problem that the quality of the selected test patterns or the fault detection rate for the fabrication test is often insufficient. Test patterns for testing functions are generated on the basis of each function being executed correctly within the design margin, but the test patterns are not generated on the basis of whether failures in circuits can be detected. In addition, since a complex LSI circuit requires an enormous amount of time to carry out a fault simulation for calculating a fault detection rate, failures are sampled for the fault simulation, or patterns are selected in conformity with the activation rate of each signal calculated through a logic simulation. In those cases, the fault detection rate cannot be calculated accurately.
A design for testability (DFT) is a technology for enhancing testing by embedding the smallest possible test circuits in LSI circuits to optimize the test pattern generation period, the test pattern size, testing time, and the ultimate fault detection rate. Typically, the design for testability includes scanning design, a memory built-in self test (BIST), and logic BIST.
The scanning design is a DFT technology, which has been widely used. All registers (flip-flops (F/Fs) or latches) within sequence circuits are replaced with dedicated registers called ‘scan registers’, which are one or more shift registers (forming a scan path) and serially connected to each other. Usage of this structure allows direct control and monitoring of registers of an internal circuit, which is usually difficult, via external input/output terminals. This allows considerable simplification in test pattern generation processing. In particular, test patterns with high fault detection rates can be generated in a short period using an automatic test pattern generation (ATPG) program.
A test circuit that uses all F/Fs except for faulty F/Fs, and prevents misjudgment of whether an LSI circuit has a failure and reduces the scan path read-out/write-in time has been disclosed (Patent Reference 1: Japanese Patent Laid-Open No. Hei 4-250371). In addition, a semiconductor LSI circuit that controls scan paths or the like and monitors test patterns even if there are some failures on a scan path has been disclosed (Patent Reference 2: Japanese Patent Laid-Open No. Hei 10-31056).
The conventional scanning design provides a plurality of individual scan paths. In a scan circuit shifting test, all memory elements belonging to those scan paths in a semiconductor LSI circuit with a conventional scan circuit are targets of failure analysis. In this case, when there are several thousands of memory devices, all of the devices are targets of failure analysis, which makes failure analysis a very difficult problem. In other words, according to the prior art, when an error is detected through a scanning and shifting test, all scan paths have been subjected to failure analysis.
In addition, according to the conventional scanning design, since circuits are generated without regard to the clock-tree structure, an element at the end of a clock tree or an upper driver therein is controlled first. For example, assume that a faulty scan element is connected to a faulty clock driver. In this case, when the clock tree has a failure, errors are found in all scan paths, which makes failure analysis difficult. Therefore, when a clock driver has a failure, errors are found in all scan paths including a scan element connected to that faulty clock driver failure analysis is very difficult.
Furthermore, a set signal and a reset signal have the same problem as in the clock tree. In other words, according to the prior art, when a structure relevant to a set signal or a reset signal has a failure, errors are found in all scan paths including a scan element connected thereto, and failure analysis is very difficult.